Regarding the consideration of the power supply signal integrity and circuit problems in PCB design, in circuit design, we are usually concerned about the quality of the signal, but sometimes we are confined to the signal line for research, and consider power and ground as ideal Although this can simplify the problem, in high-speed designs, this simplification is no longer feasible. Although the direct result of circuit design is manifested in signal integrity, we must not ignore the power integrity design. Because power integrity directly affects the signal integrity of the final PCB. Power integrity and signal integrity are closely related, and in many cases, the main cause of signal distortion is the power system. For example, the ground bounce noise is too large, the design of the decoupling capacitor is not suitable, the loop impact is very serious, the multi-power / ground plane is not well segmented, the ground layer design is not reasonable, the current is uneven, and so on. The following are divided into three points to explain in detail:
One: Decoupling capacitor:
We all know that adding some capacitors between the power supply and the ground can reduce the noise of the system, but how much capacitors are added to the circuit board? How large is the capacitance of each capacitor? Where is each capacitor better? Similar to these questions We generally don't think about it seriously, but only based on the designer's experience, and sometimes even think that the less the capacitor, the better. In high-speed design, we must consider the parasitic parameters of the capacitor, quantitatively calculate the number of decoupling capacitors, the capacitance of each capacitor, and the specific location of the capacitor to ensure that the impedance of the system is within the control range. A basic principle No decoupling capacitors are needed, no one is needed, no extra capacitors are needed.
2: Ground bounce:
When the edge rate of a high-speed device is lower than 0.5ns, the data exchange rate from the large-capacity data bus is particularly fast. When it generates strong ripples in the power layer that affect the signal, power supply instability will occur. When the current through the ground loop changes, a voltage is generated due to the loop inductance. When the rising edge is shortened, the current change rate increases and the ground bounce voltage increases. At this time, the ground plane (ground wire) is no longer the ideal zero level, and the power supply is not the ideal DC potential. As the number of gates that are simultaneously switched increases, the ground bounce becomes more severe. For a 128-bit bus, there may be 50_100 I / O lines switched on the same clock edge. At this time, the inductance of the power supply and the ground loop fed back to the I / O driver that switches at the same time must be as low as possible, otherwise, a voltage brush will appear when it is still connected to the same ground. Ground bounce can be seen everywhere, such as chips, packages, connectors, or circuit boards, which can cause ground bounces, leading to power integrity issues.
From the perspective of technology development, the rising edge of the device will only decrease, and the width of the bus will only increase. The only way to keep ground bounce acceptable is to reduce the power and ground distributed inductance. For a chip, it means moving to an array chip, placing as much power and ground as possible, and the wiring to the package as short as possible to reduce inductance. For packaging, it means moving layer packaging to make the ground plane of the power supply closer, as used in BGA packaging. For a connector, it means using more ground pins or redesigning the connector to have an internal power and ground plane, such as a connector-based ribbon cord. For a circuit board, this means placing adjacent power and ground planes as close as possible. Since the inductance is proportional to the length, making the power and ground connections as short as possible will reduce ground noise.
Three: power distribution system:
Power integrity design is a very complicated matter, but how to control the impedance between the power system (power and ground plane) in recent years is the key to the design. In theory, the lower the impedance between power systems, the better, the lower the impedance, the smaller the noise amplitude, and the smaller the voltage loss. In actual design, we can determine the target impedance we want to achieve by specifying the maximum voltage and power supply variation range, and then adjust the relevant factors in the circuit to make the impedance (frequency-dependent) target impedance of each part of the power system approach.
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